Driver for swicthing circuit and drive method

ABSTRACT

A driver circuit includes monitoring circuitry ( 32, 34, 36 ) for monitoring the states of high and low side switches ( 6, 8 ). The driver circuit has an adjustable delay for turning on the transistors ( 6, 8 ). The delay is decreased when the monitoring circuit detects that a voltage corresponding to one transistor passes a predetermined voltage V 1  before a voltage corresponding to the other transistor passes another predetermined point V 2,  and vice versa.

The invention relates to switching circuit, drive circuitry for such acircuit and a method of driving a switching circuit, and particularlybut not exclusively to a switching voltage converter circuit.

A wide variety of switching regulators are commonly used to generatevoltages.

One type of converter, a synchronous dc-dc converter, is illustratedschematically in FIG. 1. An input voltage V_(in) is applied betweeninput terminals 2,4. A pair of transistors, here field effecttransistors 6,8, are connected between the input terminals 2,4. Thetransistor 6 adjacent to the input terminal 2 is known as the controlFET or high side transistor, and the transistor 8 adjacent to the groundis known as the synchronous (sync) FET or low side transistor. The highside is relatively more positive than the low side, though it is notnecessary that either the high or the low side has any particularrelationship to ground.

The node between the transistors 6, 8 is known as the switch node 10.The switch node feeds through an inductor 12 and across a capacitor 14to an output 16.

A control circuit 18 has one input on an input control terminal 20 andanother input fed from the output 16 via a feedback path 21. The controlcircuit 18 supplies control signals to control the FETs 6,8 to maintaina constant voltage at the output by switching transistors 6,8 off and onalternately. The control signals are alternating signals which cause thecontrol and sync FETs to conduct alternately. The mark-space ratio isvaried, i.e. the ratio of the time for which the control FET conducts tothe time the sync FET conducts is modulated, to achieve the desiredvoltage on the output 16.

Examples of such dc-dc converters include those presented in WO98/49607to Intel Corporation and U.S. Pat. No. 5,479,089 to Lee.

One feature of synchronous dc-dc converters is that it is not generallydesired to switch on both high and low side transistors 6,8simultaneously. If both transistors are on, the input voltage isshort-circuited by current passing directly between the two inputterminals 2,4 through the control and sync FETs. The phenomenon is knownas “shoot-through”. Accordingly, the control circuit 18 is generallyarranged to ensure that only one of the two transistors 6,8 is on at atime.

This is conventionally carried out by monitoring two voltages. Thevoltage at the switch node 10 is monitored to prevent the switching onof the low side transistor 8 until the high side transistor 6 isswitched off. The voltage at the gate of the low side transistor 8 ismonitored to prevent the high side transistor switching on until the lowside transistor 8 is switched off. WO98/49607 describes a circuit ofthis type, as does U.S. Pat. No. 5,479,089 to Lee.

The dead time when neither FET is conducting depends on the transistorthreshold voltage and the capacitance of the sync FET, which vary widelydue to manufacturing spread of parameters of the chosen FET, as well asaccording to the individual choice of FET. This means that a control IChas to use conservative estimates of these parameters to produce a deadtime that will avoid shoot through. This is generally a longer dead timethan would be possible if the control circuit were optimised for thespecific FETs used.

The present trend is to increase switching and clock speeds, whichincreases the significance of the dead time during which neither high orlow side transistor 6,8 is on. It would be beneficial to reduce thistime.

One circuit that aims to reduce this dead time is that described inWO02/063752 to Philips. The voltage on the drive node 10 is monitoredand compared with a predetermined voltage, generally of opposite sign tothe output voltage. When the control FET 6 switches off, the inductorcontinues to draw current through the parasitic body diode of the syncFET 8. The body diode drops about 0.6V, and so assuming that the inputand output voltages are positive, the voltage at the drive node 10becomes negative when the control FET is switched off. WO02/063752accordingly uses the voltage at the drive node falling below apredetermined value to trigger the turning on of the sync FET to ensurethat the sync FET is not switched on until the control FET is switchedoff.

However, although such a circuit reliably avoids shoot through, thereremains an appreciable dead time, when neither FET is switched on, of atleast the delay time of the driver plus the turn-on time of the FET.This dead time is about 30 ns using current technology.

Another approach is described in U.S. Pat. No. 6,396,250. In thiscircuit, controllable delays are provided on the inputs to gatetransistors, controlled by a feedback loop with the signal taken fromthe switch node. The inventors have realised that although this circuitdelivers some benefits there are disadvantages from taking the controlsignal from the switch node in this way.

As switching speeds increase still further, it would be beneficial toreduce the dead time as much as possible.

Accordingly, in one aspect there is provided a drive circuit for aswitching circuit, comprising: first and second gate control outputs forconnection to the gates of respective first and second insulated gatetransistors; first and second gate drivers connected to the first andsecond gate control outputs respectively for driving the respectivegates to switch the first and second insulated gate transistors on andoff alternately; and monitoring circuitry for monitoring the voltages onfirst and second monitor points and hence the state of the first andsecond transistors respectively, the first monitor point being one ofthe first gate control output and a switch node between first and secondtransistors and the second monitor point being the second gate controloutput, wherein the drive circuitry is arranged: to drive the secondgate driver to switch off the second insulated gate transistor and thenafter a controllable delay D to drive the first gate driver to switch onthe first insulated gate transistor; to compare the time that thevoltage on the first monitor point passes a first predetermined voltageand the time that the voltage on the second monitor point passes asecond predetermined voltage; and to decrease the delay D if the secondtime is before the first time and to increase the delay D if the secondtime is after the first time.

The circuitry allows the dead time to be reduced to a minimum withoutneeding excessively complex additional circuitry.

By using timing information related to each transistor separately ratherthan by just taking a feedback signal from the switch node as in U.S.Pat. No. 6,396,250 the circuit can track the turn on times of eachtransistor in a consistent and reliable manner.

The transistors may be connected in series at a switch node. The firstmonitor point may be the switch node. Alternatively, the first monitorpoint may conveniently be the first gate. The benefits of theseapproaches will be defined in more detail below.

The delay D may be increased or decreased by a predetermined amount. Thepredetermined amount may be in the range 0.5 ns to 10 ns, preferably 1ns to 5 ns. By using a predetermined amount in this range, especially inthe preferred range, the deadtime can be reduced to zero even as changesin operating currents and temperature during operation affect theswitching time of the components—the system is capable of adjustingrapidly enough to cope with these variations. Further, this range allowsgood stability. If the delay is decreased in steps that are too large,then the gate signals may overlap to such and extend that both FETs willbe fully on and “shoot through” will occur, thus increasing losses.Therefore, the steps must be small enough to avoid significant shootthrough.

Alternatively, the delay D can be varied by a variable amount—forexample the greater the time difference between the first and secondtimes the more D may be adjusted on each cycle.

The predetermined voltages may be selected based on the components usedfor the insulated gate field effect transistors.

The first and second predetermined voltages may be in the range 1V to2V; this voltage allows good control for a variety of output voltages.In circuits operating only at higher voltage range, the predeterminedvoltages may vary more widely. For example, for a 12V output, thepredetermined voltage may be in the range 1V to 10V.

The voltages may be the same, and may preferably be at a level roughlycorresponding to the threshold voltages of the transistors.

For a p-channel insulated gate transistor, the correspondingpredetermined voltage may be 1V to 2V below the p-channel sourcevoltage.

In a preferred embodiment, the drive circuit is arranged: to switch offthe second one of the insulated gate transistors and after a seconddelay E to switch on the first one of the insulated gate transistors; tocompare the time that the voltage on the first gate control outputpasses a third predetermined voltage and the time that the voltage onthe second gate control output passes a fourth predetermined voltage;and to decrease the second delay E if the fourth time is after the thirdtime and increasing the second delay E if the fourth time is before thethird time. This enables the drive circuitry to set the delay D to bedifferent from the second delay E, thereby allowing the delays for thefirst and second transistors to be set separately.

Conveniently, the third voltage equals the first voltage and the fourthvoltage equals the second voltage.

The invention also relates to a switching circuit comprising a drivecircuit as set out above and upper and lower insulated gate transistorseach having gate, source and drain, the gates of the upper and lowerinsulated gate transistors being connected to corresponding gate controloutputs of the drive circuitry.

The predetermined voltages may be within 1V of the threshold voltage ofthe insulated gate transistors.

In embodiments, the first monitor point is the first gate controloutput. This symmetrical arrangement avoids the need for a separateconnection to the switch node, since the drive circuit has both thefirst and second gate control outputs available within it. Also, by notneeding to monitor the switch node difficulties with noise at the switchnode are avoided.

In an alternative embodiment the first monitor point is the switch node.Taking the first transistor to be the high side transistor, the sourceof the first transistor effectively floats on the oscillating switchnode voltage, meaning that the gate source voltage shifts relative toground. By monitoring the switch node instead of the gate voltage thereis no need to take account of the varying reference voltage of the highside transistor. Moreover, variations in the threshold voltage of thefirst transistor no longer need to be taken into account.

Preferably, the predetermined voltages are in the range 1V to 2V withrespect to the ground of the low side transistor—this range allows thedriver to work with as wide a range of conversion (output) voltagesrespectively.

In another aspect there is provided a switching converter circuit withcontrol and sync insulated gate transistors each having gate, source anddrain, the control and sync insulated gate transistors being connectedtogether in series with a switch node for driving a load insulated gatetransistors; and drive circuitry connected to the gates of the insulatedgate transistors for switching the control and sync insulated gatetransistors on and off alternately, wherein the drive circuitry isarranged: to switch off the sync insulated gate transistor and switch onthe control insulated gate transistors after a delay D; to monitor thevoltages at first and second monitor points, the first monitor pointbeing the switch node or the gate voltages of the control transistor andthe second monitor point being the gate voltage of the sync transistor;to compare the time that the voltage on the first monitor point fallsbelow a first predetermined voltage and the time that the voltage on thesecond monitor point rises above a second predetermined voltage; and todecrease the delay D if the second time is after the first time and toincrease the delay D if the second time is before the first time.

In a further aspect, the invention relates to a method of driving aconverter circuit having control and sync insulated gate transistorseach having gate, source and drain, the upper and lower insulated gatetransistors being connected together in series and having a switch nodetherebetween for connection to a load; the method including the stepsof: (a) switching off a first one of the insulated gate transistors; (b)switching on the second one of the insulated gate transistors after adelay D; (c) monitoring the voltages at first and second monitor points,the first monitor point being one of the gate of the first transistorand the switch node and the second monitor point being the gate of thesecond transistor; and (d) comparing the time that the voltage on thefirst monitor point passes a first predetermined voltage and the timethat the voltage on the second monitor point passes a secondpredetermined voltage; (e) decreasing the delay D if the second time isafter the first time and increasing the delay D if the second time isbefore the first time; and (f) switching on the first and secondtransistors alternately, repeating steps (a) to (e) above when switchingon the second transistor and switching off the first transistor.

For a better understanding of the invention, embodiments of theinvention will now be described, purely by way of example, withreference to the accompanying drawings, in which:

FIG. 1 shows a prior art buck converter circuit;

FIG. 2 shows a switching converter circuit according to a firstembodiment of the invention;

FIGS. 3(a) to 3(c) show voltages in the first embodiment of theinvention; and

FIG. 4 shows a second embodiment of the invention.

Referring to FIG. 2, a high-side (control) FET 6 is connected via switchnode 10 in series with a low-side (sync) FET 8 between a high-side lineconnected to high-side input terminal 2 and ground connected to low-sideinput terminal 4. Switch node 10 is connected through inductor 12 andacross capacitor 14 to output 16 which may be connected to a load. Theload may be, for example, a micro processor.

Drive circuitry 18 drives the gates 38 of the high-side 6 and low-side 8FETs. An input signal is provided on terminal 20. In this embodiment,the input signal is a pulse-width modulated signal generated by asuitable generator. The generator is not shown in the drawings sincesuitable generation schemes are well known to the skilled person. Thegeneration scheme may in particular use feedback from output 16 tocontrol the mark-space ratio of the signal input at terminal 20 andhence to control the voltage output at output 16.

A first gate driver circuit 22 and a second gate driver circuit 24 arearranged to provide suitable signals on first and second gate controloutputs 26, 28. These are connected in turn to the gates of thehigh-side FET 6 and the low-side FET 8 respectively. The gate drivers22, 24 both include circuitry to turn off the respective transistor inresponse to a signal pulse on signal input 20, and to turn on therespective transistor after a predetermined delay on receipt of theopposite sign of pulse on signal input 20. Such circuits having acontrollable turn-on delay may be made in a number of ways by theskilled person. For example, some circuits are described in U.S. Pat.No. 6,396,250 to Bridge.

First and second comparators 32, 34 are provided connected to first andsecond gate control outputs 26, 28 respectively. Each compares thevoltage on the gate output with a respective predetermined voltage andprovide a corresponding output signal to control unit 36. Comparators32, 34 and control unit 36 accordingly constitute monitoring circuitryfor monitoring gate voltages on the FETs 6, 8.

The control unit 36 is connected to the drive circuits 22, 24 to set theprogrammable turn-on delay in these circuits.

In use, when the low-side FET 8 is turned off the high-side FET 6 isturned on after a programmable delay D. The voltages on the first gatecontrol output 26 connected to high-side FET 6 is shown in FIG. 3 a as adotted line, and the corresponding voltage on second gate control output28 connected to low-side FET 8 is shown as a solid line.

In the state shown in FIG. 3 a, the delay D is sufficiently long thatthe low-side FET 8 turns off long before the high-side FET 6 turns on.In this case, control unit 36 detects that the gate voltage of low-sideFET 8 passes predetermined voltage V2 long before the voltage on firstgate control output 26 passes voltage V1. The term “first time” will beused to describe the time relating to the first transistor and the term“second time” with be used to describe the time relating to the secondtransistor, even though the order of first and second times vary, forexample in the initial state the second time is before the first time.

When the control unit 36 determines that the second time is before thefirst time the delay D is decreased by a predetermined amount of 2 ns.This is repeated on each input cycle of the signal on signal input 20,with the delay being reduced by the predetermined time 2 ns on eachcycle until the situation in FIG. 3 b is reached in which the first andsecond times are substantially the same. The voltages V1, V2 areselected so that in this state the dead time is reduced to around 1 to 2ns which represents a significantly reduced dead time compared to aconventional scheme, which includes the rise time which may typically beof order 12 ns.

As component values change with time, for example as the components warmup, the situation in FIG. 3 c may occur in which the second time isafter the first time. In this case, control circuitry 36 increases thedelay to avoid shoot-through.

A corresponding feedback loop is used to turn on the second transistorand turn off the first transistor. A separate turn-on delay E is usedfor the second transistor to take account of the component variationbetween first and second transistors 6, 8.

When the transistors are switched, the inductance of the connection,i.e. the wires and PCB, between the driver and the transistor incombination with the gate drive current will cause a voltage drop alongthe connection leading to an error in the sensed gate voltages.Therefore, in a preferred variation the sense connections of comparators32,34 may be connected directly to the insulated gates of thetransistors through separate connections to the connection carrying thegate drive current. Alternatively, in a multichip module implementationthe comparators may be integrated in the same package as the insulatedgate transistors and directly connected thereto.

In a second embodiment of the invention, the input to the firstcomparator 32 is taken from the switch node 10 instead of the firstcontrol output 26. This is shown in FIG. 4.

This works since when the high-side FET 6 is switched on the voltage onthe switch node 10 rises from about −0.5V to the input voltage. Turningoff the high-side FET 6 causes the switch node 10 to fall from the inputvoltage to about −0.5V. The reference voltage can therefore be any pointbetween 0V and the conversion voltage, but preferably between 1 and 2Vto allow the drive circuitry to work for as wide a range of conversionvoltages as possible and to give a level of noise immunity, since theswitch node 10 is inevitably noisy.

The benefit of the approach of FIG. 4 is that threshold voltagevariations of the control FET are no longer relevant. A second advantageis that the gate-source voltage of the high-side FET 6 is referenced toa source that floats high when the FET is turned on and floats low whenthe FET is turned off. This makes it more difficult to monitor the gatevoltage signal of the high-side FET 6. By monitoring the switch node asan alternative to the gate of the high-side FET there is no suchdifficulty.

From reading the present disclosure, other variations and modificationswill be apparent to persons skilled in the art. Such variations andmodifications may involve equivalent and other features which arealready known in the design, manufacture and use of the switchingcircuit and which may be used in addition to or instead of featuresdescribed herein. Although claims have been formulated in thisapplication to particular combinations of features, it should beunderstood that the scope of disclosure also includes any novel featureor any novel combination of features disclosed herein either explicitlyor implicitly or any generalisation thereof, whether or not it mitigatesany or all of the same technical problems as does the present invention.The applicants hereby give notice that new claims may be formulated toany such features and/or combinations of such features during theprosecution of the present application or of any further applicationsderived therefrom.

For example, the embodiments described use the approach of the inventionfor turning on both transistors, but it is possible to use the approachonly for turning on one transistor, and not the other.

There is no need for both the transistors to be n-channel. For example,the control FET could be p-channel. In this case, the predeterminedreference voltage would be about 1V-2V lower than the threshold voltageof this transistor.

The described embodiments use steps of constant size to reach theminimum delay. However, this is not an essential feature and the skilledperson will readily conceive of alternative approaches. For example, thesize of the step can be proportional to the difference in time betweenthe first and second times.

Further, although the described embodiments relate to a switchingvoltage converter the invention is also applicable to other switchingarrangements where switches need to be operated with a minimal delaybetween operation.

1. A drive circuit (8) for a switching circuit, comprising: first andsecond gate control outputs (26, 28) for connection to the gates ofrespective first and second insulated gate transistors (6, 8); first andsecond gate drivers (22, 24) connected to the first and second gatecontrol outputs (26, 28) respectively for driving the respective gatesto switch the first and second insulated gate transistors on and offalternately; monitoring circuitry (32, 34, 36) for monitoring thevoltages on first and second monitor points and hence the state of thefirst and second transistors (6, 8) respectively, the first monitorpoint being one of the first gate and a switch node (10) between firstand second transistors and the second monitor point being the secondgate; wherein the drive circuitry is arranged: to drive the second gatedriver (24) to switch off the second insulated gate transistor (8) andthen after a controllable delay D to drive the first gate driver (22) toswitch on the first insulated gate transistor (6); to compare the timethat the voltage on the first monitor point passes a first predeterminedvoltage and the time that the voltage on the monitor point passes asecond predetermined voltage; and to decrease the delay D if the secondtime is before the first time and to increase the delay D if the secondtime is after the first time.
 2. A drive circuit according to claim 1wherein the first monitor point is the first gate control output (26)and the second monitor point is the second gate control output (28). 3.A drive circuit according to claim 1 wherein first and second insulatedgate transistors are connected together in series at a switch node andthe first monitor point is the switch node.
 4. A drive circuit accordingto any preceding claim wherein every time the delay D is increased ordecreased it is increased or decreased by a constant predetermined time.5. A drive circuit according to claim 4 wherein the predetermined timeis in the range 1 ns to 5 ns.
 6. A drive circuit according to anypreceding claim wherein the drive circuitry is arranged: to switch offthe first insulated gate transistor (6) and after a second delay E toswitch on the second insulated gate transistor (8); to compare the timethat the voltage on the first monitor point passes a third predeterminedvoltage and the time that the voltage on the second monitor point passesa fourth predetermined voltage; and to decrease the second delay E ifthe fourth time is after the third time and to increase the second delayE if the fourth time is before the third time, so that the drivecircuitry can set the delay D to be different from the second delay E.7. A switching circuit comprising: a drive circuit (18) according to anypreceding claim; and first and second insulated gate transistors (6, 8)each having gate, source and drain, the gates (38) of the first andsecond insulated gate transistors (6, 8) being connected tocorresponding gate control outputs (26, 28) of the drive circuit.
 8. Aswitching circuit according to claim 7 wherein the predeterminedvoltages are within 1V of the threshold voltage of the insulated gatetransistors (6, 8).
 9. A switching converter circuit, comprising:control and sync insulated gate transistors (6, 8) each having gate,source and drain, the control and sync insulated gate transistors (6, 8)being connected together in series at a switch node (10) for driving aload; and a drive circuit (18) connected to the gates of the insulatedgate transistors for switching the control and sync insulated gatetransistors on and off alternately; wherein the drive circuit (18) isarranged: to switch off the sync insulated gate transistor (8) andswitch on the control insulated gate transistor (6) after a delay D; tomonitor the voltages at first and second monitoring points, the firstmonitor point being the switch node or the gate voltage of the controltransistor (6) and the second monitor point being the gate voltage ofthe sync transistor (8); to compare the time that the voltage on thefirst monitoring point falls, below a first predetermined voltage andthe time that the voltage on the second monitoring point rises above asecond predetermined voltage; and to decrease the delay D if the secondtime is after the first time and to increase the delay D if the secondtime is before the first time.
 10. A method of driving a convertercircuit having first and second insulated gate transistors (6, 8) eachhaving gate, source and drain, the method including the steps of: (a)switching off the first insulated gate transistor (6); (b) switching onthe second insulated gate transistor (8) after a delay D; (c) monitoringthe voltages at first and second monitor points, the first monitorpoints being one of the gate of the first transistor (6) and a switchnode (10) between first and second transistors, and the second monitorpoint being the gate of the second transistor (8); and (d) comparing thetime that the voltage on the first monitor point passes a firstpredetermined voltage and the time that the voltage on the secondmonitor point passes above a second predetermined voltage; (e)decreasing the delay D if the second time is after the first time andincreasing the delay D if the second time is before the first time; and(f) switching on the first and second transistors (6, 8) alternately,repeating steps (a) to (e) above when switching on the second transistorand switching off the first transistor.
 11. A method according to claim10 further comprising: (g) switching off the second insulated gatetransistor (8) and switching on the first insulated gate transistor (6)after a second delay E which may be different from the delay D; (h)monitoring the voltages at the first and second monitor points; (i)comparing the third time that the voltage on the second monitor pointfalls below a third predetermined voltage and the fourth time that thevoltage on the first monitor point rises above a fourth predeterminedvoltage; (j) decreasing the second delay E if the fourth time is afterthe third time and increasing the second delay E if the fourth time isbefore the third time; and repeating steps (g) to (j) above whenswitching on the first transistor (6) and switching off the secondtransistor (8) as the transistors are switched on alternately.
 12. Amethod according to claim 10 or 11 wherein the delay is increased ordecreased by a predetermined amount in the range 1 ns to 5 ns on eachcycle.
 13. A method according to any of claims 10 to 12 wherein thefirst monitor point is the gate of the control transistor respectively.14. A method according to any of claims 10 to 12 wherein the first andsecond insulated gate transistors (6, 8) are connected together inseries and have a switch node (10) therebetween for connection to aload, and in which the first monitor point is the switch node.